1. Field of the Invention
This invention relates generally to the field of electronic circuits and more specifically to universal logic circuit cells and modules that can be used to lay out many complex combinatorial logic circuits with a minimum of interconnecting wiring, unused connections and unused space. The invention will find greatest use on integrated circuits, but it can also find utility in circuits implemented in more discrete form on a printed circuit board.
2. Description of the Prior Art
In recent years, it has become common to use read-only memories and programmable logic arrays to implement combinatorial logic functions as substitutes for combinatorial logic circuits that would otherwise be quite irregular and which could consume considerable amounts of space on an integrated circuit chip. For example, combinatorial logic used in the feedback paths of finite state machines is often highly complex and irregular. See, for example, Mead and Conway, Introduction to VSLI Systems, Addison Wesley (1980), at pages 79-82. Read only memories have been used as a substitute for combinatorial logic to generate predetermined output signals based on selected patterns of input signals. The input signals constitute address signals that identify one storage location, the contents of which contain a number of bits each of which corresponds to one of the required output signals.
A further benefit arises from the use of read only memories and programmable logic arrays, namely, that these elements can be readily changed during the checkout phase of product development, whereas combinatorial logic circuits implementing similar functions cannot be so readily changed without substantial revisions in circuit layout.
It is common, however, for a circuit to not require all of the addressable locations that would be identified by the input signals. In an actual circuit, the actual number of different combinations of input signals that may be encountered may be far fewer than would otherwise be represented by the number of input signals present. Further, in some instances, some of the input signals may not contribute to the selection of a location. Accordingly, providing one storage location for each possible combination of input signals may also consume considerable amounts of unnecessary space on an integrated circuit chip. Programmable logic arrays alleviate some of the problems inherent in read only memories by allowing many of the unnecessary circuits to be eliminated.
However, programmable logic arrays, particularly those used to implement arithmetic functions such as adders, adder/subtractors, fraction point shifters, and the like, often also take up substantial amounts of unnecessary space on a chip. Typically, programmable logic arrays comprise two spacially segregated arrays, an input array that comprises AND gates and an output array comprising OR gates that receive signals from the AND array and generates the output signals therefrom. Typically, the input signals to the AND array are complemented or inverted, and both the non-inverted and the inverted signals run throughout the array, which increases the amount of space on the chip taken up by the array.
Another problem that arises with programmable logic arrays, in part because of the segregation of the AND and OR functions into separate arrays, is that it may be difficult to check the connections to verify that the desired output signals are generated for every possible combination of input signals. For example, while it may be known that a logic operation should include an Exclusive-OR function, that function may not be readily apparent from examining a programmable logic array circuit.